1. Field of the Invention
The present invention relates to a semiconductor device having a capacitive element such as a DRAM and a method of manufacturing the same.
2. Description of the Prior Art
Along with increases in capacitances of semiconductor memories in recent years, the memory cell area continues to shrink. Under the circumstances, structures for increasing the charge storage amounts of capacitive elements without increasing their planar layout areas have been proposed. A stacked type capacitive element is one of such devices, and is constituted by a lower electrode formed on a semiconductor substrate, a capacitive insulating film formed on the surface of the lower electrode, and an upper electrode so formed as to cover the lower electrode via the capacitive insulating film. In this capacitive element, however, the opposite area of the lower and upper electrodes is determined on the basis of the upper and side surface areas of the lower electrode. Therefore, to increase the capacitance without increasing the upper surface area, the lower electrode must be made thick.
A technique based on such a technical concept is disclosed in Japanese Unexamined Patent Publication No. 4-332161. FIG. 1 is a schematic sectional view showing this technique. An element isolation insulating film 32, a gate insulating film 33, and a gate electrode 34 are formed on a semiconductor substrate 31. After the gate electrode 34 is covered with a first insulating film 35, a second insulating film 36 formed on the resultant structure is selectively etched to form an opening. When a lower electrode 37 is deposited on a region including this opening, the lower electrode 37 portion at the opening end portion of the second insulating film 36 is made thicker than the remaining portion. The lower electrode 37 is etched at its thick portion to expose a side surface corresponding to the thickness of that portion. A capacitive insulating film 38 and an upper electrode 39 are formed on this side surface to oppose each other, thereby completing a capacitive element. With this structure, the charge storage amount is increased.
In the technique described in this prior art, however, the lower electrode 37 itself is made thick, resulting in a difficulty in fine etching process. In addition, when the lower electrode 37 is to be etched, the etching end portion must be aligned with respect to the opening end portion of the second insulating film 36, and this aligning operation is difficult. If a degradation in process accuracy, or a misalignment occurs, the side surface area of the lower electrode 37 tends to vary, and the designed capacitance value can hardly be obtained. The lower electrode 37 tends to sharply project upward near the etching end portion. This projecting portion may be easily damaged in a later process. In addition, the steep step makes it difficult to obtain a capacitive insulating film 38 or an upper electrode 39 having a uniform thickness. Particularly, the capacitive insulating film 38 cannot be satisfactorily formed at the acute-angled portion, resulting in a decrease in dielectric strength or a short circuit between the upper and lower electrodes. Since the projecting portion degrades the surface planarity of the semiconductor device, disconnection in the upper interconnect tends to occur.